Tunable transconductance-capacitance filter with coefficients independent of variations in process corner, temperature, and input supply voltage

ABSTRACT

A transconductance-capacitance (G m -C) filter of arbitrary order is provided that is biased by a bias circuit such that the G m -C filter is robust to variations in process corner and temperature as well as input supply noise. The bias circuit includes a biased transistor that has a width-to-length ratio that is a factor X times larger than a corresponding transistor in the G m -C filter. The biased transistor couples to ground through a switched capacitor circuit.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 12/848,006, filed on Jul. 30, 2010, which is incorporatedherein by reference in its entirety.

TECHNICAL FIELD

The present invention relates generally to filters, and moreparticularly to tunable transconductance-capacitance (G_(m)-C) filters.

BACKGROUND

Transconductance-capacitance (G_(m)-C) filters offer attractiveperformance characteristics. Thus, the use of G_(m)-C filters iswidespread and pervasive in radio communications and signal processing.Analog G_(m)-C filters are constructed using operationaltransconductance amplifiers (OTAs). OTAs operate to translate a voltageinput signal into a current output signal. An example balanced(differential output) OTA is shown in FIG. 1 a. The transconductanceG_(m) for the OTA determines the I⁺ and I⁻ currents based upon the inputvoltages V⁺ and V⁻ according to the following equations:

I ⁺ =G _(m)(V ⁺ −V ⁻)

I−G _(m)(V ⁻ −V ⁺)

Various approaches are known to construct OTAs such as using cascodes ordifferential architectures. A simple analog transconductance-capacitance(G_(m)-C) filter may be constructed using a single-ended OTA as shown inFIG. 1 b. If a time constant τ is defined as C₁/G_(m), then it can beshown that V_(in) for this filter equals V_(out)+τ d(V_(out)(t)/dt. Thecutoff frequency for the resulting G_(m)-C filter will thus rely on bothG_(m) and C₁. But process corner variations will typically be in therange of 20% for a desired capacitance whereas a desiredtransconductance will have process corner variations in the range of10%. It follows that the resulting time constant τ for such a filterwill be accurate to just 30% across all the process corner variations.Moreover, transconductance values will vary significantly withtemperature and the supply voltage level. In addition, input noise willintroduce variations in the filter coefficients. Accordingly, it isconventional to provide some sort of tuning circuitry on G_(m)-Cfilters. In this fashion, a tunable G_(m)-C filter has its time constantset to some desired value with some isolation from variations in thepower supply voltage, process corner, and temperature.

Although such independence is desirable, conventional tunable G_(m)-Cfilters are still sensitive to power supply variations and suffer fromnon-idealities. Accordingly, there is a need in the art for improvedtunable G_(m)-C filters that are more robust to variations in processcorner, power supply, and temperature.

SUMMARY

In accordance with one aspect of the invention, atransconductance-capacitance (G_(m)-C) filter is provided that includes:a plurality of operational transconductance amplifiers (OTAs), wherein afirst one of the OTAs has a first transconductance and the remainingones of the OTAs have transconductances that are proportional to thefirst transconductance, and a bias circuit for biasing the firsttransconductance to a desired value responsive to a clock frequency, thebias circuit including a switched capacitor circuit generating aresistance inversely proportional to the clock frequency, wherein thedesired transconductance value is proportional to the clock frequency.

In accordance with another aspect of the invention, atransconductance-capacitance (G_(m)-C) filter is provided that includes:a plurality of operational transconductance amplifiers (OTAs), whereineach OTA includes a differential pair of transistors providing a tailcurrent to a third transistor having a transconductance g_(m), and abias circuit for biasing a gate of a given one of the third transistorswith a control voltage, the bias circuit including a switched capacitorcircuit such that a transfer function for the G_(m)-C filter isproportional to a ratio of capacitances and is independent of processcorner variations.

In accordance with yet another aspect of the invention, a bias circuitto bias the transconductance g_(m) of a first transistor within aG_(m)-C filter is provided that includes: a second transistor having awidth-to-length ratio that is a factor X larger than a width-to-lengthratio of the first transistor, the second transistor coupling to groundthrough a switched capacitor circuit such that g_(m) is proportional to(1−1/X^(1/2)).

The scope of the invention is defined by the claims, which areincorporated into this section by reference. A more completeunderstanding of embodiments of the present invention will be affordedto those skilled in the art, as well as a realization of additionaladvantages thereof, by a consideration of the following detaileddescription of one or more embodiments. Reference will be made to theappended sheets of drawings that will first be described briefly.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 a is a schematic diagram of an operational transconductanceamplifier (OTA).

FIG. 1 b is a schematic diagram of a conventionaltransconductance-capacitance (G_(m)-C) filter.

FIG. 2 is a schematic diagram of a biquad G_(m)-C filter tuned using aswitched-capacitor bias circuit.

FIG. 3 is a circuit diagram of a differential amplifier within an OTA inthe filter of FIG. 2.

FIG. 4 a is a circuit diagram illustrating the equivalence of a switchedcapacitor circuit to a resistor.

FIG. 4 b is a circuit diagram of a switched capacitor circuit adaptedfor greater robustness to parasitic effects.

FIG. 5 is a circuit diagram for a bias circuit to provide the controlvoltage applied in the circuit of FIG. 3.

Embodiments of the present invention and their advantages are bestunderstood by referring to the detailed description that follows. Itshould be appreciated that like reference numerals are used to identifylike elements illustrated in one or more of the figures.

DETAILED DESCRIPTION

Reference will now be made in detail to one or more embodiments of theinvention. While the invention will be described with respect to theseembodiments, it should be understood that the invention is not limitedto any particular embodiment. On the contrary, the invention includesalternatives, modifications, and equivalents as may come within thespirit and scope of the appended claims. Furthermore, in the followingdescription, numerous specific details are set forth to provide athorough understanding of the invention. The invention may be practicedwithout some or all of these specific details. In other instances,well-known structures and principles of operation have not beendescribed in detail to avoid obscuring the invention.

To provide a tunable G_(m)-C filter that self-compensates with regard toprocess corner variations, power supply variations, and temperaturevariations, a switched capacitor circuit is used to tune thetransconductance G_(m) of one of more of the OTAs included within theG_(m)-C filter. In that regard, a biquad second order G_(m)-C filtersuch as filter 100 shown in FIG. 2 includes five different OTAs, eachhaving their own independent transconductance (denoted as g_(m1) throughg_(m5)). In addition, filter 100 includes 3 classes of capacitors(having corresponding capacitances C₁ through C₃). The transfer functionH(s) for filter 100 thus depends on the various transconductances andcapacitances as given by the following equation:

$\begin{matrix}{\mspace{79mu} {{H(s)} = {{\frac{{s^{2}\left\lbrack \frac{\text{?}}{\text{?} + C_{2}} \right\rbrack} + {\text{?}\left\lbrack \frac{\text{?}}{C_{2} + C_{2}} \right\rbrack} + \left\lbrack \frac{G_{m\; 2}G_{m\; 4}}{C_{1}\left( {\text{?} + C_{2}} \right)} \right\rbrack}{s^{2} + {s\left\lbrack \frac{\text{?}}{C_{2} + C_{2}} \right\rbrack} + \left\lbrack \frac{G_{m\; 1}G_{m\; 2}}{C_{1} + \left( {C_{2} + C_{2}} \right)} \right\rbrack}.\text{?}}\text{indicates text missing or illegible when filed}}}} & (1)\end{matrix}$

This relatively complex behavior can be simplified as follows. Althoughtransconductances have large variations in their absolute values,relative transconductance values can be set quite accurately by theratio of the OTA transistor widths (provided the same channel lengthsare used for all devices). Thus, an arbitrary OTA such as OTA 105 havinga transconductance g_(m1) may be used to define the transconductance ofthe remaining OTAs. For example, the transconductance g_(m2) for OTA 110may be defined as K_(m2)g_(m1), the transconductance g_(m3) for OTA 115may be defined as K_(m3)g_(m1), and so on. In general, the ithtransconductance can be expressed in terms of the first OTA as

G _(mi) =K _(mi) G _(mi)  (2)

Similarly, the sum of the capacitances C₃ and C₂ can be defined in termsof C1 using a constant K as

C ₃ +C ₂ =KC ₁  (3)

Using equations (2) and (3), equation (1) can be simplified as follows

$\begin{matrix}{\mspace{79mu} {{H(s)} = {{\frac{{s^{2}\left\lbrack \frac{\text{?}}{\text{?} + C_{2}} \right\rbrack} + {{s\left( \frac{\text{?}}{K} \right)}\left( \frac{G_{m\; 1}}{C_{1}} \right)} + {\left( \frac{K_{m\; 2}K_{m\; 4}}{K} \right)\left( \frac{G_{m\; 1}}{C_{1}} \right)^{2}}}{s^{2} + {{s\left( \frac{\text{?}}{K} \right)}\left( \frac{G_{m\; 1}}{C_{1}} \right)} + {\left( \frac{K_{m\; 1}K_{m\; 2}}{K} \right)\left( \frac{G_{m\; 1}}{C_{1}} \right)^{2}}}.\text{?}}\text{indicates text missing or illegible when filed}}}} & (4)\end{matrix}$

From equation (4), it can be seen that if just the ratio of Gm1/C1 istuned to be self-compensating with regard to variations in power supply,process corner, and temperature, then the remainingtransconductance/capacitance ratios need no tuning since these ratioscan be conventionally manufactured to an accuracy of approximately onepercent.

Although the above simplification was described with regard to thebiquad filter 100 of FIG. 1, it can be shown that any order (nth order)of G_(m)-C filters can be tuned in this fashion. In other words, asingle one of the OTAs may be self-compensated as discussed furtherherein yet the entire G_(m)-C filter will be self-compensated. Thisself-compensation may be better understood with reference to thetransistor differential pair within each OTA. An example differentialpair of matched transistors M1 and M2 is shown in FIG. 3. The tailcurrent from transistor M1 and M3 is biased by a control voltageV_(cntl) driving the gate of a transistor M3. Matched transistors M1 andM2 each have a transconductance of G_(n), whereas M3 is sized to have atransconductance of AG_(m).

The following discussion will show how to generate the bias voltageV_(cnt1) such that the ratio of G_(m)/C_(L) for the OTA isself-compensating. This self compensation will rely on the use of aswitched capacitor circuit to produce a desired resistance. As knownfrom Ohm's law, a voltage potential V_(A)−V_(B) applied across aresistor of resistance R will produce a current I equaling(V_(A)−V_(B))/R. However, as seen in FIG. 4 a, the same amount of chargecan be moved between these voltage potentials using a switched capacitorcircuit 400 that couples voltage V_(A) to a capacitor having acapacitance C_(ck) through a switch S₁. Similarly, the capacitor couplesto voltage V_(B) through a switch S₂. If switched S₁ is driven on andoff by a clock of frequency f_(ck) while switch S₂ is driven by thecomplement of this clock, it can be shown that a current I flowingthrough the capacitor will equal f_(ck)C_(ck)(V_(A)−V_(B)). Thus, theswitched capacitor circuit functions as a resistor having a resistanceR_(m) of

R _(m)=1/f _(ck) C _(ck).  (5)

The equivalence of a switched capacitor circuit to provide a desiredresistance is made more precise by using the additional switches S₃ andS₄ as shown in FIG. 4 b for a switched capacitor circuit 405 in that theadditional switches make the circuit parasitic insensitive. S₁ and S₄are driven by the clock whereas S₂ and S₃ are driven by the complementof the clock.

The incorporation of a switched capacitor circuit into a bias circuit500 as shown in FIG. 5 for the generation of the control voltageV_(cnt1) will now be discussed. A pair of PMOS transistors P₁ and P₂form a current mirror. Thus, if P₁ and P₂ are matched (same width W andlength L and thus the same W/L ratio), they will each source the samecurrent I. Thus, a current I flows through an NMOS transistor M₄ and anNMOS transistor M₅. M4 is diode connected between the drain of a PMOStransistor P₁ and ground so as to be in saturation mode. Transistor M₄is matched to M₃ of FIG. 3. The gate of M₄ is tied to the gate oftransistor M₅, where M₅ is larger than M₄. If M₅ has the same length Las does M₄, then the width of M₅ is a factor X times larger than a widthW for M₄. The sources of both P₁ and P₂ are driven by a power supplyvoltage node V_(CC). The source of M₅ couples to ground through aswitched capacitor circuit 505 that functions to provide a resistance ofR_(m). It can be shown that the transconductance g_(m4) for M₄ can beexpressed as

g _(m)=2/R _(m)(1−1/Sqrt(X))  (6)

Substitution of equation (5) into equation (6) allows thetransconductance to be expressed as

g _(m4)=2(1−1/Sqrt(X))f _(ck) C _(ck)  (7)

It will be appreciated that the switched capacitor circuit 505 may bemade more robust as discussed with regard to FIG. 4 b. Examination ofequation (7) shows that the transconductance dependence on the width Xis such that by making X sufficiently large, the necessary clockfrequency for driving the switched capacitor circuit is reduced. This isa substantial advantage over other techniques used to make G_(m)-Cfilters more robust to variations in power supply voltage (input noise),process corners, and temperature.

Referring back to FIG. 3, one can see that if the transconductance of M₃is controlled by the control voltage V_(cnt1) generated as discussedwith regard to FIG. 5, the ratio of G_(m)/C_(L) for the OTA/capacitorcombination including such a differential pair can be expressed as

G _(m) /C _(L)=2A(1−1/Sqrt(X))f _(ck) C _(ck) /C _(L)  (8)

Referring again to FIG. 2, suppose that the OTAs were all matched in thesense of having matched differential pairs of transistors as discussedwith regard to FIG. 3. It has already been shown with regard to equation(4) that if just one of the transconductances is tuned, then the overallG_(m)-C for the filter is established. As seen by equation (8), thefilter coefficients will depend only on the ratio of device parametersand capacitances. This is quite advantageous as the resulting filtercoefficients will be independent of process and temperature variationsas well as power supply noise. For example, a fast process corner willaffect C_(ck) equally as it does affect C_(L). Thus, the ratio ofcapacitances cancels out process corner variations. The same argumentapplies to temperature and power supply noise. Moreover, although thisself compensation of a G_(m)-C filter has been discussed with regard tothe biquad filter 100 of FIG. 2, the same self-compensation can beapplied to any nth order G_(m)-C filter.

It will be obvious to those skilled in the art that various changes andmodifications may be made without departing from this invention in itsbroader aspects. The appended claims encompass all such changes andmodifications as fall within the true spirit and scope of thisinvention.

I claim:
 1. A bias circuit to bias the transconductance g_(m) of a firsttransistor within a G_(m)-C filter, comprising: a second transistorhaving a width-to-length ratio that is a factor X larger than awidth-to-length ratio for the first transistor, the second transistorcoupling to ground through a switched capacitor circuit such that g_(m)is proportional to (1−1/X^(1/2)).
 2. The bias circuit of claim 1,wherein a gate of the first transistor is biased by a control voltagethat equals a gate voltage for the second transistor.
 3. The biascircuit of claim 2, wherein the switched capacitor circuit is driven bya clock and a complement clock of frequency f_(ck) and has a capacitorof capacitance C_(ck), whereby the switched capacitor circuit provides aresistance of 1/f_(ck)C_(ck).
 4. The bias circuit of claim 3, whereinthe control voltage drives a gate of a third transistor that matches thefirst transistor.
 5. The bias circuit of claim 4, wherein the thirdtransistor is diode connected.
 6. The bias circuit of claim 5, wherein adrain of the first transistor couples to a source of a diode-connectedfourth transistor, a drain of the fourth transistor coupling to a powersupply voltage node.